Virtual Memory and TLB Miss Penalty

A high-performance server processor employs a 2-level TLB hierarchy (L1 and L2) ahead of a 4-level page table walk in virtual memory. An application processing massive Edge AI datasets experiences an L1 TLB miss rate of 5% and an L2 TLB miss rate of 20% (of the misses reaching it). If an L1 TLB hit takes 1 cycle, an L2 TLB hit takes 5 cycles, and one page walk takes 100 cycles, what is the average memory access time (AMAT) for address translation alone?