WORST Case Sizing

You are designing a standard cell for a 3nm process. A complex CMOS logic gate implements the Boolean function Y = ~(A + BC). Assuming all NMOS transistors are sized 'W' and PMOS are sized '2W' for an equivalent reference inverter (to balance rise/fall times), what should be the worst-case sizing of the PMOS transistors in the pull-up network to perfectly match the rise time of the reference inverter?