Clock Tree Network Power

After Clock Tree Synthesis (CTS), an H-tree network distributes a 2GHz clock to 100,000 flip-flops across a die. The extracted total capacitance of the entire clock network (including all buffers, wire routing, and sink pins) is 500pF. If the core operates at a nominal voltage of 0.8V, what is the dynamic power consumed strictly by toggling this clock network?