Memory Hierarchy and Page Table Walk

A system features a 48-bit virtual address space, a 40-bit physical address space, and a 4KB page size. The translation lookaside buffer (TLB) is a 4-way set associative cache with 512 total entries. If a memory reference results in a TLB miss but a page table hit, and the system implements a 4-level hierarchical page table where each page table entry (PTE) is 8 bytes, how many memory accesses are required to fetch the data word from the physical memory, assuming no other caches (L1/L2) are present?