Hold Time Violation with Clock Skew

A data path between two flip-flops has a combinational propagation delay of 40 ps. The launching flip-flop has a Tclk to Q minimum delay of 30 ps. The capturing flip-flop has a hold time requirement (Thold) of 50 ps. The clock network exhibits a positive skew where the capture clock edge arrives 35 ps later than the launch clock edge. Assuming no OCV derates, what is the hold slack, and is there a violation?