Scan Shift Power Budgeting

During normal functional mode, a digital block toggles 15% of its flip-flops per cycle at a 1GHz clock frequency. During DFT scan shift, the toggle rate explodes to 50% per cycle. To prevent dynamic IR drop from causing setup failures during test, the test engineer must cap the scan shift frequency so that the average dynamic power perfectly matches the functional mode power. Assuming voltage and capacitance are constant, what must the scan test clock frequency be?