System Verilog Looping (Overflow/Rollover Concept)
What will be the behavior of the above SystemVerilog code?
module tb;
initial begin
bit [3:0] i; //i = 0 to 15
for(i = 0; i < 16; i++) begin
#1ns;
$display("i %0b", i);
end
end
endmodule
What will be the behavior of the above SystemVerilog code?
module tb;
initial begin
bit [3:0] i; //i = 0 to 15
for(i = 0; i < 16; i++) begin
#1ns;
$display("i %0b", i);
end
end
endmodule