System Verilog - class operators

Guess the output of thew below system verilog Code

// Code your testbench here
// or browse Examples
class parent;
  
  int i;
endclass

class child extends parent;
  
  int j;
endclass


module tb;
  
  parent p = new();
  child c = new();
  
  initial begin
    p.i = 3;	
    c.j = 5; 
    
    p = c;
    
    p.i = 6;
    
    $display("c.i : %0d , c.j : %0d", c.i, c.j); 
  end
endmodule