Logic Inference

 Consider the following RTL:

always @(posedge clk or negedge resetn) begin
    if (!resetn)
        q1 <= 1'b0;
    else
        q1 <= d;
end

always @(posedge clk or negedge resetn) begin
    if (!resetn)
        q2 <= 1'b1;
    else
        q2 <= d;
end

Can the synthesis tool safely merge q1 and q2 into one physical register?