Time available

In a design, FF1 is clocked by CLK on the rising edge, and FF2 is clocked by the falling edge of the same CLK. The clock period is 4 ns. The clock has a 40% duty cycle (high for 1.6 ns, low for 2.4 ns). For a data transfer from FF1 to FF2, what is the effectively available time for the combinational logic (ignoring setup, clock-to-Q, and skew)?