Setup Slack Calculation With Jitter

In a synchronous digital circuit, two flip-flops (FF1 to FF2) operate on a 1 GHz clock (Tclk = 1000ps). The timing parameters are:

• Clock-to-Q delay (Tcq): 150ps

• Combinational logic delay (Tlogic): 650ps

• Setup time requirement (Tsetup): 80ps

• Clock Skew (Capture edge delay - Launch edge delay): -50ps (Capture clock arrives 50ps early)

• Clock Jitter constraint: 40ps

  Calculate the setup slack for this path.