PMOS Width

You are sizing an AOI22 complex logic gate (And-Or-Invert) which implements the function Y = ~((AB) + (CD)). To achieve equal worst-case rise and fall delays comparable to a standard unit inverter (where PMOS width = 2, NMOS width = 1), what should be the width of each PMOS transistor in the pull-up network? (Assume mobility µn = 2*µp).