CMOS Power
As CMOS technology scales down deep into the sub-micron regime (e.g., 7nm, 5nm), which of the following mechanisms becomes a heavily dominant contributor to the overall static power dissipation of a chip?
As CMOS technology scales down deep into the sub-micron regime (e.g., 7nm, 5nm), which of the following mechanisms becomes a heavily dominant contributor to the overall static power dissipation of a chip?