Shift Register
Consider the following Verilog code snippet. What is the fundamental issue if this is intended to model a multi-bit shift register?
always @(posedge clk) begin
q[0] = d;
q[1] = q[0];
q[2] = q[1];
endConsider the following Verilog code snippet. What is the fundamental issue if this is intended to model a multi-bit shift register?
always @(posedge clk) begin
q[0] = d;
q[1] = q[0];
q[2] = q[1];
end