Sequential Modelling
When modeling sequential logic (e.g., flip-flops) inside a Verilog always @(posedge clk) block, why is it standard practice to use non-blocking assignments <=) instead of blocking assignments =)?
When modeling sequential logic (e.g., flip-flops) inside a Verilog always @(posedge clk) block, why is it standard practice to use non-blocking assignments <=) instead of blocking assignments =)?