Pipelining

Consider a 5-stage RISC pipeline (IF, ID, EX, MEM, WB) without data forwarding. If the instruction sequence is ADD R1, R2, R3 followed immediately by SUB R4, R1, R5, how many stall cycles are required to ensure the correct value of R1 is used? Assuming register write happens on positive edge of clock and register read happens on negative edge of clock.