Pipeline Hazards and Forwarding

Scenario: Consider a standard 5-stage RISC pipeline (IF, ID, EX, MEM, WB) with full data forwarding logic. Examine the following code sequence:

LDR  R1, [R2, #0]  ; Load R1 from memory at address R2
ADD  R3, R1, R4     ; R3 = R1 + R4
STR  R3, [R5, #0]  ; Store R3 to memory at address R5

Which of the following statements is TRUE regarding stalls and forwarding in this sequence?