Pipeline Depth
A processor increases its pipeline depth from 12 to 20 stages to achieve a higher clock frequency. If the branch misprediction rate remains constant at 5%, what is the most significant impact on the IPC (Instructions Per Cycle)?
A processor increases its pipeline depth from 12 to 20 stages to achieve a higher clock frequency. If the branch misprediction rate remains constant at 5%, what is the most significant impact on the IPC (Instructions Per Cycle)?