Physical Design - Cross-Corner Clock Skew
A balanced clock tree is synthesized for an SoC at the TT (Typical-Typical) process corner, achieving a pristine near-zero clock skew. However, during Multi-Mode Multi-Corner (MMMC) signoff, analysis at the FF (Fast-Fast) corner reveals massive clock skew leading to widespread hold violations. What is the primary physical phenomenon causing this tree balance to break across corners?