NMOS Width

You are sizing a static CMOS compound gate implementing the logic function F = (a. (b + c))’. A standard unit inverter has an NMOS size of W/L = 2 and a PMOS size of W/L = 4. To achieve a worst-case pull-down transition time equal to that of the unit inverter, what must the NMOS widths (Wa, Wb, Wc) be, assuming L is constant?