LRU

An Edge AI accelerator features a 4-way set associative L1 cache using a strict True LRU (Least Recently Used) replacement policy. A matrix multiplication kernel repeatedly loops through 5 distinct memory blocks (Block A, B, C, D, and E). Due to unfortunate address aliasing, all 5 blocks map to the exact same cache set. Assuming the cache is initially empty, what will the cache hit rate be after 100 iterations of accessing the sequence A-B-C-D-E (500 total accesses)?