Logical Equality
In Verilog, how would the logical equality ==) and case equality ===) operators evaluate the comparison 4'b101x 4'b101z and 4'b101x = 4'b101z respectively?
In Verilog, how would the logical equality ==) and case equality ===) operators evaluate the comparison 4'b101x 4'b101z and 4'b101x = 4'b101z respectively?