Half Cycle Path

A circuit uses a half-cycle path where data is launched on the rising edge of a 4.0 ns period clock and captured on the very next falling edge. Assuming a 50% duty cycle, Tcq = 0.5 ns, and Tsetup = 0.2 ns (with ideal clocks and zero skew), what is the maximum allowable combinational delay (Tcomb) between the registers?