Flip Flop synthesis
Consider the following Verilog code intended to model a two-stage pipeline register. What is the most likely synthesis result for q1 and q2?
always @(posedge clk) begin
q1 = d; // Stage 1
q2 = q1; // Stage 2
endConsider the following Verilog code intended to model a two-stage pipeline register. What is the most likely synthesis result for q1 and q2?
always @(posedge clk) begin
q1 = d; // Stage 1
q2 = q1; // Stage 2
end