CMOS Dynamic Power Dissipation

A CMOS logic block operates at a supply voltage (VDD) of 1.0V and a clock frequency of 2 GHz. The total switched load capacitance is 50 fF. The activity factor (α), which represents the probability of a 0-to-1 transition per clock cycle, is 0.2. Assuming short-circuit and leakage power are negligible, what is the dynamic switching power consumed by this block?