CDC
A fast clock domain (CLK_A, 1 GHz) sends a single-cycle pulse to a slow clock domain (CLK_B, 100 MHz). A standard 2-flop synchronizer is used. What is the most likely failure scenario?
A fast clock domain (CLK_A, 1 GHz) sends a single-cycle pulse to a slow clock domain (CLK_B, 100 MHz). A standard 2-flop synchronizer is used. What is the most likely failure scenario?