Asynchronous FIFO Depth Calculation

An asynchronous FIFO is used to bridge data crossing from Clock Domain A (fa = 400MHz) to Clock Domain B (fb = 150MHz). There are no idle cycles during a burst. The burst size is 120 words. The write side can perform 1 write every clock cycle, while the read side can perform 1 read every 3 clock cycles. What is the minimum depth of the FIFO required to prevent any data overflow?