Physical Design - Basics
Why is Physical Design Important?
Logic synthesis gives us a gate-level representation of the design, but a chip cannot be manufactured directly from a netlist. Physical Design converts this logical representation into an actual physical layout, determining where the cells are placed and how they are connected.
The decisions made during Physical Design have a direct impact on performance, power, area, reliability, and manufacturability of the final chip. Therefore, achieving a good physical implementation is essential for a design to successfully reach fabrication.
Where Does Physical Design Fit in the ASIC Flow?
Physical Design primarily comes after Logic Synthesis and before final Physical Verification and Signoff.
RTL → Synthesis → Physical Design → Physical Verification & Signoff → GDSII → Foundry
Physical Design starts with the synthesized netlist along with technology libraries, constraints, and other design inputs. It produces the final physical layout through stages such as Floorplanning, Placement, CTS, and Routing, which is then taken through signoff before being sent to the foundry.
1. Floorplanning
This defines the chip's overall layout — placement of macros, memory blocks, I/O pads, and power planning. It sets the die size, core area, and creates the power grid (rings and straps) that will supply the entire chip.
2. Placement
Standard cells are placed into rows within the core area based on connectivity and timing requirements. It's usually done in two steps — global placement (rough positioning) and detailed placement (legalization, fixing overlaps) — with the goal of minimizing wirelength and congestion.
3. Clock Tree Synthesis (CTS)
A clock distribution network (tree) is built to deliver the clock signal to all sequential elements (flip-flops) with minimal skew and latency. Buffers/inverters are inserted along the tree to balance clock arrival times across the chip.
4. Routing
Actual metal connections (wires) are drawn between all the placed cells according to the netlist, using multiple metal layers. This includes global routing (rough paths) and detailed routing (exact tracks), while honoring design rules (DRC).
What is PPA Optimization?
PPA stands for Power, Performance, and Area, the three fundamental metrics used to evaluate and optimize a digital design.
Power: Minimize the power consumed by the chip while maintaining functionality.
Performance: Meet the required timing constraints and achieve the target operating frequency.
Area: Minimize the silicon area required to implement the design.
These parameters are closely related, and improving one can often affect the others. Physical Design therefore involves finding the right trade-offs between power, performance, and area.
Goals of Physical Design
The primary goal of Physical Design is to obtain a physically correct, manufacturable, and optimized layout while satisfying all design constraints.
Key goals include:
Achieve timing closure and meet performance requirements.
Optimize power and area.
Maintain power integrity and signal integrity.
Make the chip reliable and robust so that it has a higher life time in all conditions.
Satisfy physical and manufacturing rules.
Produce a final layout that is ready to be sent to the foundry for fabrication.