Course Contents

Introduction About the Course

In this Physical Design course, you will learn the concepts involved in transforming a synthesized digital design into a physical layout suitable for manufacturing. The course covers the ASIC design flow, Physical Design fundamentals, implementation stages, signoff, and practical design challenges.

Level 1: Introduction

Understanding the ASIC design flow, what Physical Design is, why it is important, and its role in achieving Power, Performance, and Area (PPA) goals.

Level 2: Fundamentals

Introduction to ASIC design inputs, technology and design files, physical-only cells, and logic synthesis, along with the fundamentals of RTL-to-hardware mapping and synthesis optimization.

Level 3: Physical Design Implementation

Covers the major implementation stages: Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing, with emphasis on their objectives, optimization, and common design challenges.

Level 4: Physical Verification, Signoff & ECO

Understanding the key physical verification and signoff checks, including DRC, ERC, LVS, LEC, IR drop, EM, antenna checks, and ECO techniques.

Level 5: Scenario-Based & Advanced Concepts

Application of Physical Design concepts through scenario-based questions, along with selected advanced topics such as double patterning and IC fabrication fundamentals.

Level 6: Projects

Hands-on application of the concepts through practical RTL-to-GDSII projects. Projects will cover complete physical implementation flows, hierarchical design, architectural comparisons for PPA, and low-power implementation techniques. Additional projects will be introduced to provide exposure to different design challenges, architectures, and optimization techniques.