ASIC Design Flow
An ASIC design progresses through a series of stages that transform a functional specification into a physical chip ready for manufacturing. Each stage generates the required inputs for the next stage while progressively refining and verifying the design.
1. Specification
The required functionality and design targets such as performance, power, area, cost, and technology are defined. These requirements guide all subsequent design decisions.
2. Architecture Design
The overall architecture of the chip is defined, including major functional blocks, data paths, control logic, memory organization, and interfaces. Architectural decisions establish the structure and behavior of the final design.
3. RTL Design
The architecture is converted into an RTL description using HDLs such as Verilog or SystemVerilog. RTL describes the digital logic, data flow, and sequential behavior of the design.
4. Functional Verification
The RTL is simulated and verified to ensure that it meets the intended functionality. Testbenches and verification methodologies are used to detect and debug functional errors.
5. Logic Synthesis
The verified RTL is converted into a technology-mapped gate-level netlist using the target standard-cell libraries. The synthesis tool optimizes the logic based on constraints such as timing, area, and power.
6. Design for Test (DFT)
Test structures such as scan chains, test points, and other DFT logic are inserted into the design. These structures enable efficient testing of manufactured chips for defects.
7. Physical Design
The synthesized netlist is transformed into a physical layout. The design is floorplanned, placed, clocked, and routed while optimizing timing, power, area, congestion, and other physical constraints.
8. Physical Verification & Signoff
The physical layout is checked to ensure that it satisfies manufacturing, electrical, and timing requirements. Checks such as DRC, LVS, ERC, STA, IR drop, and EM are performed before final signoff.
9. GDSII Generation
Once the design passes signoff, we generate the final GDSII database containing the physical geometries of the chip. This is the layout information that we provide to the foundry for manufacturing.
10. Fabrication
The foundry uses the GDSII data to create the required photomasks and manufacture the chip on semiconductor wafers. Processes such as lithography, deposition, etching, and doping are used to form the transistors and interconnects. .
11. Packaging & Testing
The fabricated dies are packaged to provide electrical connections and mechanical protection. The packaged chips are then tested to verify their functionality and performance before being released.
Below is the complete flowchart of ASIC design flow and various steps involved in making a chip. We have further expanded steps involved in Physical Design specifically about which we are learn in depth in next blog.
