Verilog Questions
Master hardware design with Verilog. Practice hardware design and synthesis problems.
| # | Status | Name | Language | Difficulty | Companies | Action |
|---|---|---|---|---|---|---|
| 1 | Traffic Light Controller with Pedestrian Request fsm | Verilog | Medium |   | ||
| 2 | Priority Encoder with Valid Flag | Verilog | Medium | |||
| 3 | Rising Edge Detector | Verilog | Easy |   | ||
| 4 | 4-bit Up Counter with Asynchronous Reset | Verilog | Easy | | ||
| 5 | D Flip Flop with Asynchronous Reset | Verilog | Easy |  | ||
| 6 | D Flip Flop with Synchronous Reset | Verilog | Easy | | ||
| 7 | Cosmic Ray Shield: Hamming SECDED Codec | Verilog | Hard | | ||
| 8 | Abyss Buffer: Sonar Data FIFO Controller | Verilog | Hard | | ||
| 9 | Sequence Detector — "101" Sequence Detector | Verilog | Medium | | ||
| 10 | AXI-Stream Skid Buffer | Verilog | Hard | | ||
| 11 | Round-Robin Arbiter with Priority Override | Verilog | Medium | | ||
| 12 | Abyss-1 Explorer | Verilog | Medium | |||
| 13 | Mars Rover | Verilog | Medium | | ||
| 14 | Tomasulo Reservation Station Entry | Verilog | Hard | | ||
| 15 | LRU (Least Recently Used) Cache | Verilog | Medium | | ||
| 16 | World Cup Final | Verilog | Hard | |||
| 17 | Second Largest Number | Verilog | Medium | | ||
| 18 | Binary to Gray Conversion | Verilog | Medium | | ||
| 19 | Arithmetic Logic Unit (ALU) | Verilog | Easy | | ||
| 20 | Triangular Wave Generator | Verilog | Hard | | ||
| 21 | Divisible by 5 | Verilog | Hard | | ||
| 22 | Priority Encoder - 3bits | Verilog | Hard | | ||
| 23 | Verilog Operators | Verilog | Easy | |||
| 24 | Verilog Data Types | Verilog | Easy | |||
| 25 | Verilog Hello World | Verilog | Easy | |||
| 26 | Mux using 2*1 Mux | Verilog | Easy | |||
| 27 | Decoder - gate, data flow and behavioral design | Verilog | Easy | |||
| 28 | UNIVERSAL GATE - NOR | Verilog | Easy | |||
| 29 | UNIVERSAL GATE - NAND logic gates | Verilog | Easy | |||
| 30 | Frequency Divider by 6 | Verilog | Easy | | ||
| 31 | Frequency Divider by 4 | Verilog | Easy | |||
| 32 | Frequency Divider by 3 | Verilog | Easy | |||
| 33 | Frequency Divider by 2 | Verilog | Easy | |||
| 34 | Full Adder | Verilog | Easy | |||
| 35 | Number of 1's | Verilog | Easy | |||
| 36 | Fibonacci Sequence Generatorc | Verilog | Easy | |||
| 37 | Negative Edge Detector | Verilog | Easy | | ||
| 38 | Positive Edge Detector | Verilog | Easy | |||
| 39 | Odd value counter | Verilog | Easy | | ||
| 40 | MUX | Verilog | Easy | |||
| 41 | karnaugh map | Verilog | Easy | |||
| 42 | AND Gate | Verilog | Medium |